Sample Point Validation: Phase Segments 1/2 Tuning & Resynchronization Jump Width (SJW)
Configuring microcontroller bit timing registers to optimize the receiver sample point (typically 80%) and tolerate clock oscillator drifts.
A CAN bit consists of four non-overlapping segments: Synchronization Segment (Sync_Seg), Propagation Segment (Prop_Seg), Phase Buffer Segment 1 (Phase_Seg1), and Phase Buffer Segment 2 (Phase_Seg2). The sample point occurs between Phase_Seg1 and Phase_Seg2.
In automotive production, low-cost ceramic resonators can experience clock frequency drift of up to ±1.58% across temperature extremes (-40°C to +125°C). Validation suites sweep transmitter clock frequencies while monitoring receiver bit error counters, optimizing the Synchronization Jump Width (SJW) to ensure stable frame reception even under maximum oscillator divergence.